1. Field of the Invention
The present invention relates to a circuit board having a generally flat surface and a semiconductor device embedded therein and to a method of manufacturing the circuit board.
2. Related Art of the Invention
With the development of electronic appliances of high performance and small in size, there has been an increasing need to improve the packaging density and functions of circuit components. Also with respect to modules incorporating circuit components, there has been a demand for the capability of improving the packaging density and functions. Presently, there is a tendency to form circuit boards in a mutilayer structure in order to mount the circuit components and improve package density. In particular, a multilayer circuit board using the connection by inner vias has been put to use as a means of increasing the packaging density of a circuit. Further, there has been advanced development of a component incorporation type of circuit board capable of saving space in terms of mount area and connecting short wiring patterns between LSIs or component parts.
An example of a process for manufacturing a conventional component incorporation type of circuit board (See Japanese Patent Application Laid-Open Gazette No. 2002-204049. The disclosure of the document is incorporated herein by reference in its entirety.) will be described with reference to FIGS. 15 to 23. FIG. 15 is a cross-sectional view of a state in which a mold release layer 10 is formed on the entire area of one surface of a carrier 1 made of copper and a circuit pattern forming material 2 is formed on the mold release layer 10 by electroplating. As a material for the mold release layer 10, Cr, Ti or the like is used. As the circuit pattern forming material 2, copper, tin, zinc, nickel or gold, for example, is used. As shown in FIG. 16, a resist 3 is provided on the circuit pattern forming material 2 and formed into a desired circuit pattern by using a photolithography technique. As shown in FIG. 17, the circuit pattern forming material 2 is formed into a circuit pattern 12 by etching. Thereafter, as shown in FIG. 18, the layer of the resist 3 on the formed circuit pattern 12 is removed.
Then, as shown in FIG. 19, an electroconductive adhesive 7 is applied to projecting electrodes 6 made of an electroconductive material and formed on electrode pads of a bare semiconductor element 8, the bare semiconductor element 8 is thereafter mounted on the circuit pattern 12, and the electroconductive adhesive 7 is cured by heating. Thereafter, as shown in FIG. 20, an insulating resin 9 is injected into the gap between the bare semiconductor element 8 and the carrier 1 and is set to strengthen the connection between the projecting electrodes 6 and the circuit pattern 12.
Then, as shown in FIG. 21, an electrical insulating layer 4 is provided and through holes 15 are formed in the electrical insulating layer 4 and are filled with a via paste to form vias 5. Thereafter, as shown in FIG. 22, the carrier 1 on which the circuit pattern 12 is formed and the electrical insulating layer 4 in which the vias 5 are formed are superposed one on another while being aligned in predetermined positions, followed by heating and pressing. The bare semiconductor element 8 and the circuit pattern 12 are thereby embedded in the electrical insulating layer 4.
Finally, as shown in FIG. 23, the carrier 1 is separated after setting of the electrical insulating layer 4 to form a circuit board 40 in which the bare semiconductor element 8 and the circuit pattern 12 are embedded in the electrical insulating layer 4 and the surface of which is formed generally uniformly.
The above-described conventional method of forming the circuit pattern 12 on the carrier 1 by etching, however, necessarily includes the step of first forming the layer of circuit pattern forming material 2 on the carrier 1. The number of process steps is thereby increased, resulting in a reduction in productivity. Moreover, damage to the carrier 1 may be caused due to etching variation to considerably reduce the performance of transfer of the circuit pattern into the electrical insulating layer 4, resulting in failure to perform transfer with stability.
That is, even if the concentration of the etching solution is made uniform, there is a possibility of the etching solution unnecessarily strongly acting on the circuit pattern 12 due to the density non-uniformity of the circuit pattern 12. In such a case, there occurs not only removal of the circuit pattern forming material 2 to be etched but also erosion caused by the etching solution of the mold release layer 10 formed between the carrier 1 and the circuit pattern forming material 2. Further, even part of the carrier 1 under the mold release layer 10 may be eroded.
If part of the carrier 1 is eroded, the electrical insulating layer 4 enters the eroded region in the carrier 1 in the step shown in FIG. 22. In such a case, the electrical insulating layer 4 enters irregularities in the surface of the eroded carrier 1 to be physically combined with the carrier 1. This means that a large force is required to separate the carrier 1 from the electrical insulating layer 4 and an unnecessary force is applied to the circuit pattern 12 to separate part of the circuit pattern 12 together with the carrier 1 in the step shown in FIG. 23.